library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity miniband is
Port ( 
HB: in std_logic;
banderaN : in std_logic;
banderaZ : in std_logic;
banderaV : in std_logic;
banderaC : in std_logic;
busdatosbaja : out std_logic_vector (7 downto 0));

end miniband;

architecture Behavioral of miniband is
constant s0 : std_logic_vector(3 downto 0) := B"0000";
begin
process(HB)
begin
if HB = '1'
	then busdatosbaja <= "ZZZZZZZZ";
elsif HB ='0'
	then busdatosbaja <= s0 & banderaN & banderaZ & banderaV & banderaC;
end if; 
end process;

end Behavioral;